Decreasing device size has been the main driving force for technology advancements in the semiconductor industry over the last several decades. For example, in front end of line (FEOL) applications in semiconductor processing, junction depths have been scaled continuously together with the gate lengths in order to achieve faster transistor speeds and higher packing densities. Typically, source/drain extension junction depths of about one third of the transistor gate length have been used for efficient electrostatics and acceptable leakage currents. With gate lengths fast approaching the sub-10 nm regimes, development work is focused on reliably making sub-5 nm ultrashallow junctions (USJs) with low sheet resistivity to facilitate the future scaling of transistors.
Most commonly, USJs are commercially fabricated by the combination of ion implantation and spike annealing. During the process, Si atoms are displaced by energetic dopant ions and a subsequent annealing step (e.g. spike, a high temperature anneal process of less than 1 s with fast temperature ramp up/down capability) is used to activate the dopants by moving them into the appropriate lattice positions and restoring the substrate's crystal quality. Unfortunately, point defects such as Si interstitials and vacancies are also generated, which interact with the dopants to further broaden the junction profile—called transient-enhanced diffusion (TED), which limits the formation for sub-10 nm USJs by conventional technologies.
Significant research efforts have been made to develop new strategies to manufacture <5 nm USJs which utilize heavier implantation dopant sources (molecular implantation, gas cluster ion beam, and plasma doping) to obtain shallower doping profiles, and advanced annealing techniques (flash and laser) to activate the implanted dopants without causing significant diffusion. However, problems relating to the effects of advanced doping and annealing techniques on junction uniformity, reliability and subsequent process integration continue to hamper their use in IC manufacturing.
One potential route for achieving the USJs, while maintaining controlled doping of semiconductor materials with atomic accuracy, at such small scales, takes advantage of the crystalline nature of silicon and its rich, self-limiting surface reaction properties. This method relies on the formation of self-assembled monolayers of dopant-containing molecules on the surface of crystalline Si followed by the subsequent thermal diffusion of dopant atoms via rapid thermal annealing (RTA).
Ground-breaking work in this area has been performed by Professor Ali Javey at Berkeley (Nature Materials, vol. 7, January 2008, pp 62-67; Nanoletters, 2009 Vol. 9, No 2, pp 725-730). Dr. Javey and his group successfully doped silicon wafers by treating the Si surfaces with a dopant dissolved in mesitylene (the dopant being allylboronic acid pinacol ester for p-doped wafers, and diethyl-1-propylphosphonate for n-doped wafers), and subsequently annealing the material to diffuse the dopant atoms into the surface and achieve the n+/p USJs. Dr. Javey's results were confirmed by SIMS, and penetration depth for P-containing mixtures were observed to be ˜3-3.5 nm.
Problems remain to be solved with the Javey process though. For example, the mesitylene-containing treatment solutions used by Dr. Javey are not appropriate for commercial applications where high surface modification reaction temperatures are employed and commercial-scale material handling considerations are important. Accordingly, a need remains for improvements to Dr. Javey's method for doping silicon substrates. The present invention addresses that need.